This invention relates to reducing the effect of transients on integrated circuit operation, and more particularly to reducing on-chip power rail perturbations and the effect of power rail perturbations on the operation of high speed digital integrated circuits.
Power rail perturbation is a transient condition found on the on-chip power distribution lines, most commonly V.sub.cc and ground, of certain types of high speed digital integrated circuits. The condition arises during the switching of high current or high power circuits of the integrated circuit, due to the interaction of parasitic inductances with localized power surges. One type of power rail perturbation, ground bounce, occurs when the potential of the internal ground of the device changes relative to system ground. A related condition involving internal V.sub.cc is known as V.sub.cc squeeze. Ground bounce alone, V.sub.cc squeeze alone, or the combination of both cause spurious states and transitions to occur in the switched circuits as well as the other circuits coupled to the switched circuits, thereby corrupting retained data or causing spurious states or transitions to be transmitted in the output.
The major source of parasitic inductance is in the leads of an integrated circuit package. IC package leads commonly are obtained from leadframes such as those illustrated in FIGS. 1 through 4. The plastic dual in-line package (PDIP) leadframe 10 of FIG. 1 includes leads 12a-12x and a tiebar 14 (also known as a paddle support bar) supporting paddle 16. Also illustrated are leadframe rails 2a and 2b, and dambars 4a and 4b which form a leadframe perimeter from which the leads extend inwardly toward the integrated circuit die. Die 18 is mounted to the paddle 16, and the circuits are connected to the leads 12 with bondwire. For example, internal ground and V.sub.cc are connected to respective leads 12l and 12x through bondwires 17 and 19.
Occasionally, a tiebar is connected to supply for pulling charge out of the substrate of the mounted die, which is coupled to the tie bar through the supported paddle. An example of a suitable leadframe is illustrated in FIG. 2. The leadframe of FIG. 2 corresponds to the leadframe 10 of FIG. 1 in all respects but for ground lead 12l, which is integrally coupled to tie bar 14b by lead segment 11.
Occasionally, the paddle of a leadframe is supported by tiebars running to the dambars at the sides of the leadframe, in addition to the tiebars running to the rails at the ends of the leadframe. The practice is common for very large packages such as the 64 lead PDIP package, because end tiebars alone lack sufficient rigidity to adequately support the die throughout the various manufacturing steps. An example is illustrated in FIG. 3. The leadframe of FIG. 3 corresponds to the leadframe 10 of FIG. 1 in all respects but for the addition of tiebars 34a and 34b.
The ceramic dual in-line package (CDIP) leadframe 20 of FIG. 4 includes leads 22a-22x. Ground and power commonly are supplied through leads 22l and 22x respectively. Tiebars and paddles are not used in CDIP leadframes.
Although all leads have some impedance, the impedance of the longest leads, for example leads 12a, 12l, 12m and 12x of the PDIP leadframe 10; and leads 22a, 22l, 22m and 22x of of the CDIP leadframe 20, exhibit the greatest impedance. Unfortunately, by convention the ground and V.sub.cc pins are usually placed at corners of an IC package, and must connect to the die through the relatively long hence leads 12l and 12x of the PDIP leadframe 10, and leads 22l and 22x of the CDIP package 20.
Consider the lead model of FIG. 5, which generally represents any lead of an IC package. The lead model includes the self-inductance of the bondwire L.sub.bw, the lead self-inductance L.sub.lf, and the lead resistance R.sub.lf. An abrupt change in the current flowing through the lead 30 will induce a voltage across lead 30 due to L.sub.bw and L.sub.lf (assuming R.sub.lf negligible), in accordance with the expression ##EQU1## The voltage v(t) also may include components resulting from transients in adjacent leads, which algebraically contribute to the total voltage drop across the lead and bondwire. These components are equal to the product of the mutual inductance between the lead and an adjacent lead, and the di/dt of the adjacent lead.
Where lead 30 is a power lead, for example ground lead 12l or V.sub.cc lead 12x of the PDIP leadframe of FIG. 1, a large di/dt is likely to occur in a high performance device. The voltage at the die is the algebraic sum of the voltage at the outside end of the lead and v(t).
Certain integrated circuits are known to be affected by voltage perturbations on the power rails of the chip, due to voltage transients across the package leads. In the buffered ECL switch, for example, emitter followers are included to render the output voltage levels of the basic ECL switch compatible with the input of the following switch, to isolate the collector nodes from load capacitance, and to provide current gain. The collectors of the transistors in the emitter followers are returned to a separate V.sub.cc lead, to insure that any changes in load currents during switching do not cause a change in V.sub.cc of the basic ECL switch through the small but finite inductance of the emitter follower bondwire and package lead. Outside the package, the two V.sub.cc leads are connected to the common V.sub.cc distribution, requiring an additional pin. See. e.g., Fairchild Camera and Instrument Corporation, ECL Data Book, 1977, pp. 2-3, 2-4.